1. Field of the Invention
The present invention relates to a layout design apparatus for a semiconductor device which automatically performs a design for the placement, routing, etc. of circuit elements in a logical circuit such as an LSI, a print board or the like, and more particularly to a layout design apparatus having a delay error improving (reducing) function.
2. Description of the Related Art
In general, a layout design for the placement and routing of circuit elements in a logical circuit such as an LSI (large scale integrated circuit), ULSI (ultra large scale IC), a print board or the like is performed by a CAD (computer aided design) using a computer. This type of CAD system (hereinafter referred to as "layout design apparatus") performs not only a layout design of a logical circuit, but also a delay analysis to check whether the designed logical circuit satisfies a delay-time requirement which is based on various factors such as synchronization, etc.
In conventional layout design apparatuses as described above, an automatic placement and routing processing which aims to shorten the total length of routing and enhance routing performance is performed on the basis of logical connection information of a logical circuit. When a delay error of a path occurs during a delay analysis after an placement and routing process, the placement and the routing are manually corrected, or the logical connection information is corrected to retry the layout design, thereby eliminating the delay error.
Further, the gates on paths which have severe delay restriction are manually arranged to be adjacent to one another in advance so that the delay restriction is not violated, or in some cases the routing is manually performed, thereby reducing the delay error.
There has been also proposed a layout design apparatus for reducing the delay error by using an automatic placement and routing means having a delay analyzing means. In this type of layout design apparatus, the delay error is reduced without altering the logical connection relation of a logical circuit by improving the placement of circuit elements and a method of routing processing, etc. Such techniques are disclosed in Japanese Laid-open Patent Application No. Hei-4-279976, No. Hei-5-40802, No. Hei-5-120377, No. Hei-5-181938, etc.
There is now considered a circuit construction having a logical connection relation as shown in FIG. 9, in which flip flops 201 and 202 and gates 203 to 206 are arranged and these elements (blocks in FIG. 9) are connected to one another through nets 207 to 214. This logical circuit has a path 215 as a path among the flip flops (hereinafter referred to as an inter-flip-flop path). FIG. 17 shows a result which is obtained by performing a lay-out design on the basis of a conventional layout design apparatus.
Specifically, FIG. 17 shows the result which is obtained by performing an placement and routing work on the blocks of the flip flops 201, 202 and the gates 203 to 206, the connection routing of the input/output terminals of these blocks, the input/output routing from the external to these blocks, and the path 215 for these blocks on the basis of the input information in consideration of the conditions, logical connection information such as the number of inputs, the number of outputs, gain and loss, fan-in and fan-out, an input/output logical value, a permissible power source voltage, etc., physical information such as the occupation area of each block, etc. By the placement/routing connection work, routing results 301 to 308 shown in FIG. 17 are obtained. In this placement, the horizontal line of the routing is crooked at the routing result 304 as shown in FIG. 17. Further, the path 215 between the flip flops 201 and 202 is similarly crooked.
As described above, according to the conventional layout design apparatus, the layout design is performed on the basis of only the logical connection information and physical information. Accordingly, if through a delay analysis on an placement and routing result shown in FIG. 17 the delay restriction required to the logical circuit concerned is violated, the manual correction work of the placement and routing or the alteration of the logical connection information as described above must be carried out to retry the placement and routing processing in order to obtain an placement and routing result which satisfies the delay restriction.
As described above, the conventional layout design apparatus performs the placement and routing processing on the basis of only the logical connection information and physical information, and thus a path delay error may occur in a path having a severe delay time restriction through the delay analysis after the placement and routing process.
The delay error thus occurring is manually corrected, or the logical connection information is corrected, or an placement and routing work is beforehand manually performed in consideration of the delay restriction on a critical path to which occurrence of a delay error is expected. Therefore, a large number of steps are required for the logical correction work, the placement and routing work and the correction work of the placement and routing.
Still further, since the delay error is reduced by using the automatic placement and routing means having the delay analysis means with no logical alteration, the improvement (reduction) of the delay error has a limitation.